PURPOSE: To decide whether or not a layout pattern is good in an early stage by comparing the virtual wiring length of each signal line or its delay value with the real wiring length or its delay value.

CONSTITUTION: A virtual wiring length file output means, a real wiring length file output means, and a comparing means are executed through software in a virtual delay logical simulation step 3, an automatic arrangement wiring step 4, and a wiring length comparison step 8. In the stage of, for example, virtual delay logical simulation, the virtual wiring length of each signal line or its delay value is outputted and after layout pattern generation, the real wiring length of each signal line or its delay value is outputted. The result of a comparison between the both indicates whether or not the layout pattern is good and real wiring length delay logical simulation can be omitted when the difference between the real wiring length of each signal line or its delay value and the virtual wiring length or its delay value is within a certain permissible range.