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Patent Searching and Data


Title:
RECEIVER
Document Type and Number:
Japanese Patent JP2006332857
Kind Code:
A
Abstract:

To provide a receiver with a downsized receiver body whose cost is reduced, wherein the time until the reception of a selected channel is actually started, after a user switches channels has started.

The receiver 1 stores a channel table to a memory of a control section 2, the channel table being a table, wherein each of channels whose frequency bands includes no particular frequency being an integral multiple of a frequency of an operating clock is cross-referenced with the particular frequency. A clock generating section 7 divides the frequency of a system clock to generate the operating clock for operating a decode section 4. Thus, when a channel is selected, the operating clock for the decode section 4 appropriate to receive the channel can immediately be determined, and it is not required to provide a plurality of oscillation circuits for supplying the operating clock to the decode section 4, resulting in that the receiver body can be downsized and the cost can be reduced.


Inventors:
HITONISHI ATSUSHI
ADACHI KAZUTERU
Application Number:
JP2005150855A
Publication Date:
December 07, 2006
Filing Date:
May 24, 2005
Export Citation:
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Assignee:
FUNAI ELECTRIC CO
International Classes:
H03J5/02; H04B1/10; H04N5/44; H04N7/173