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Title:
RECEIVING DATA TRANSFER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5694425
Kind Code:
A
Abstract:

PURPOSE: To improve the processing efficiency to cause the channel device to write receiving data during the reading of the central processing unit for contents of the data buffer, by causing the central processing unit to transfer receiving data onto the main memory efficiently when the traffic quantity is increased specially.

CONSTITUTION: Central processing unit 1 reserves plural data buffer areas 10 on main memory 2 and transfers address information of these buffer areas 10 to data buffer address holding part 8 of channel device 3 and transfers received data to receiving buffers 7-0W7-N. When data is transferred by the control of direct memory access DMA control part 6, one address information of buffer area 10 which is idle is extracted, and received data is written in memory 2 by DMA control while processing unit 1 reads data in buffer area 10 according to this address information, thus improving the processing efficiency.


Inventors:
YAMAMOTO NOBORU
OKADA KENICHI
SASAKI SHINJI
Application Number:
JP17367779A
Publication Date:
July 30, 1981
Filing Date:
December 27, 1979
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/10; G06F3/00; G06F13/00; G06F13/28; (IPC1-7): G06F3/00; G06F3/04



 
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