To provide a reconfigurable circuit appropriately transferring data with an external buffer upon suspension of an internal operation.
The reconfigurable circuit includes: a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units; a suspension control circuit configured to control execution and suspension of operation of the reconfigurable arithmetic execution unit array; and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.
SUDO SHINICHI
JP2007004338A | 2007-01-11 | |||
JP2008090360A | 2008-04-17 | |||
JP2007128124A | 2007-05-24 | |||
JP2007004338A | 2007-01-11 |
Akinori Yamaguchi
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