Title:
RECONSTRUCTIBLE PSEUDO ANALOG ELECTRIC CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2000331113
Kind Code:
A
Abstract:
To obtain a reconstructible pseudo analog electric circuit device by making the mode of processing or operation in a FPG appropriately settable.
In a reconstructible pseudo analog electric circuit device 10, first and second analog signals (a) and (b) are converted into PWM signals by zero offset and variable offset, respectively. The two PWM signals are inputted to a field programmable gate array(FPGA) 16 and the FPGA 16 makes logical operation on the PWM signals by setting cells 18 and their connection in the FPGA 16 by means of a computer 22. The results of the logical operation are restored into analog signals by means of an integration circuit 20 and output analog signals (x) are obtained.
Inventors:
KANETANI ICHIRO
HENMI HITOSHI
SHIMOHARA KATSUNORI
HENMI HITOSHI
SHIMOHARA KATSUNORI
Application Number:
JP14049199A
Publication Date:
November 30, 2000
Filing Date:
May 20, 1999
Export Citation:
Assignee:
ATR NINGEN JOHO TSUSHIN KENKYU
NIPPON TELEGRAPH & TELEPHONE
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06G7/12; (IPC1-7): G06G7/12
Attorney, Agent or Firm:
Yoshito Yamada