PURPOSE: To make it possible to check redundant codes without storing redundant codes in a controlling memory by generating redundant codes for controlling data by a redundant code checking mechanism and storing them in a random access memory.
CONSTITUTION: Parity bits for controlling data stored in a controlling memory 20 are formed by a redundant code checking mechanism 4 and stored in a random access memory 23. When accessing the controlling memory 20, controlling data stored in the controlling memory 20 and parity bits stored in the random access memory 23 are read out and inputted to the redundant code checking mechanism 4 and parity check is performed. Thus, a ROM for parity bit becomes unnecessary and manufacturing cost of the controlling memory 20 is reduced.
| WO/2016/018210 | DETECTION OF ABNORMAL TRANSACTION LOOPS |
| WO/2014/178855 | MEMORY NODE ERROR CORRECTION |
| JPH10228388 | DATA ERROR DETECTION CIRCUIT |
TSUCHIYA HARUHIKO
YOSHIOKA TORU
