PURPOSE: To contrive the improvement of the reduction of an apparent dynamic RAM by jumping the RFC of row address by the data of control RAM read out by RF address at the time of a refreshing RF cycle C.

CONSTITUTION: When reading or writing data from a bus 1 to a dynamic RAM 4, an address switching circuit 3 divides input address into a row address RA and a column address and outputs them to the RAM 4 and a switching circuit 8. The circuit 8 switches RA from the circuit 3 so as to input it to a control RAM 7, and the RAM 7 writes a contents corresponding to the RA to 1. Then, at the time of RFC, the circuit 3 and the circuit 8 are switched to an RF address line 2, and an RF control circuit 9 outputs an address to be refreshed to the line 2. Then the RAM 7 reads out the contents corresponding to input address from the line 2. When the content read out by the RAM 7 is 1, the circuit 9 stops the RF of the address at the time of RFC of the RAM 4, and improves the apparent lowering of access time of the RAM 4.