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Patent Searching and Data


Title:
RESIST DEVELOPMENT DEVICE
Document Type and Number:
Japanese Patent JPH01125828
Kind Code:
A
Abstract:

PURPOSE: To prevent the yield and the quality of an integrated circuit element from deteriorating due to the plasma damage by providing a means exposing the peripheral part of a semiconductor substrate.

CONSTITUTION: The peripheral part of a wafer 1 vacuum-sucked by a wafer chuck 8 is firstly exposed by a peripheral exposure device 11 before development process. A shade 12 is provided to be fixed to an upper cup 7 or not to expose the inner part of the wafer 1 i.e. the already exposed part on an integrated circuit element pattern so that the peripheral exposure device 11 may expose only the resist pad part 31 on the peripheral part of the wafer 1. Consequently, it is needless to pay attention to the resist pad part 31 on the peripheral part of the wafer 1 in the ordinary exposure process so long as the exposure process is performed meeting the requirements for the film thickness of a resist 3 on the true integrated circuit element at the central part of the wafer 1. Through these procedures, plasma peeling off time can be cut down to decrease the damage due to plasma and prevent the yield and the device charateristics from deteriorating.


Inventors:
TAKAHASHI SHIGERU
NOZUE HIROSHI
SHINTOMI HIROYUKI
Application Number:
JP28491687A
Publication Date:
May 18, 1989
Filing Date:
November 10, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
G03F7/20; H01L21/027; H01L21/30; (IPC1-7): G03F7/20; H01L21/30
Attorney, Agent or Firm:
Uchihara Shin