Title:
RESIST PATTERN FORMING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME, AND RESIST SURFACE LAYER TREATING AGENT
Document Type and Number:
Japanese Patent JP2004103926
Kind Code:
A
Abstract:
To provide a method for forming a resist pattern, along with a material used for forming the resist pattern, for stably forming a fine resist pattern of high aspect ratio.
A resist film 1 is formed on a silicon wafer W. After exposure with an exposure mask M, a post-exposure baking is performed. The silicon wafer W after post-exposure baking is formed with a resist surface layer treating agent film 2, and then applied with a mixing baking. A resist reinforced part R is formed by the mixing baking. Then non-reacted part 2a is removed before the silicon wafer W is dried. The silicon wafer W is plasma-dry-developed to form a wanted resist pattern.
Inventors:
ISHIBASHI TAKEO
Application Number:
JP2002265429A
Publication Date:
April 02, 2004
Filing Date:
September 11, 2002
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G03F5/00; G03F7/038; G03F7/075; G03F7/11; G03F7/36; G03F7/38; G03F7/40; H01L21/027; (IPC1-7): H01L21/027; G03F7/11; G03F7/36; G03F7/38
Attorney, Agent or Firm:
Shigeaki Yoshida
Yoshitake Hidetoshi
Takahiro Arita
Yoshitake Hidetoshi
Takahiro Arita