RETICLE AND PRODUCTION OF SEMICONDUCTOR DEVICE

Title:

RETICLE AND PRODUCTION OF SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JP2001022051

Kind Code:

A

Abstract:

To improve the accuracy in the measurement of superposition accuracy.

This reticle is provided with a chip region which is within a projection range of an exposure device and is formed with semiconductor circuit patterns and a plurality of marks for measurement for measuring the superposition accuracy in a scribe line region which is the region exclusive of the chip region. The marks for measurement are composed of plural main patterns 114 which are arranged apart a prescribed pitch 111 along the measurement direction (121) of the superposition accuracy and auxiliary patterns 113 and 115 which are made equal in the pitch 112 with the first pattern described above to the prescribed pitch 111 described above. The resist patterns corresponding only to the plural main patterns are formed and the formed resist patterns are subjected to the measurement of the superposition accuracy by the constitution described above.

Inventors:

FUJIMOTO TADASHI

Application Number:

JP19676699A

Publication Date:

January 26, 2001

Filing Date:

July 09, 1999

Export Citation:

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Assignee:

NEC CORP

International Classes:

H01L21/027; G03F1/42; G03F9/00; (IPC1-7): G03F1/08; H01L21/027

Attorney, Agent or Firm:

Nobuo Takahashi (3 outside)

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