Title:
SAMPLED AMPLITUDE READ CHANNEL AND DIGITAL DATA READ METHOD
Document Type and Number:
Japanese Patent JPH1092118
Kind Code:
A
Abstract:
To realize a discrete time filter of a higher order and an analog filter of a lower order by using a sampling read channel which is provided with a sampling device, with an adaptive equalizer, with a restriction circuit and with a discrete time sequence detector.
In a sampled amplitude read channel, an interpolated timing recovery B100 is provided instead of a conventional sampling timing recovery. In addition, a write frequency synthesizer 52 generates a baut rate write clock 54 which is given to a write circuit 9. A sampling device 24, a discrete time equalizer filter B103 and the interpolated timing recovery B100 generate an asynchronous read clock 54 which is clock-matched at a frequency CDR 30 with reference to a present zone.
Inventors:
SPURBECK MARK S
DU LI
TRENT DUDLEY O
BLISS WILLIAM G
FEYH GERMAN S
BEHRENS RICHARD T
DU LI
TRENT DUDLEY O
BLISS WILLIAM G
FEYH GERMAN S
BEHRENS RICHARD T
Application Number:
JP10640997A
Publication Date:
April 10, 1998
Filing Date:
April 23, 1997
Export Citation:
Assignee:
CIRRUS LOGIC INC
International Classes:
G11B5/09; G11B20/10; G11B20/14; G11B20/18; H03H15/00; H03H17/02; H03H17/06; H04L25/03; G11B5/012; G11B5/035; H04L7/00; H04L7/02; (IPC1-7): G11B20/14; G11B5/09; G11B20/18; H03H15/00; H03H17/02; H03H17/06; H04L25/03
Attorney, Agent or Firm:
Shusaku Yamamoto