Title:
SAMPLING CIRCUIT AND CORRELATION ARITHMETIC UNIT USING THE CIRCUIT
Document Type and Number:
Japanese Patent JP3243664
Kind Code:
B2
Abstract:
PURPOSE: To suppress the dispersion of data generated at the time of sampling an inputted noisy signal.
CONSTITUTION: An input signal is integrated by an integrating circuit 40 to obtain voltage proportional to the deviation of a low frequency component, and after adjusting the phase of the voltage by a phase shifting circuit, the phase-shifted voltage is impressed to a comparating point of a samplier 3. The value '1' of output data from the samplier 3 is counted up by a counter circuit 11, data corresponding to the number of counts are read out from a PROM 13 and A/D converted and the converted digital data are applied to the circuit 40 to compensate the asymmetry of a high frequency component in the input signal. Consequently the dispersion of data at the time of their sampling can be suppressed, and when the sampling circuit is used for a radio interferometer, a correlation value can be accurately calculated and an image can be prevented from being deteriorated at the time of its synthesis.
Inventors:
Tatsuya Ito
Application Number:
JP5163193A
Publication Date:
January 07, 2002
Filing Date:
March 12, 1993
Export Citation:
Assignee:
NEC Engineering Co., Ltd.
International Classes:
G06G7/19; H03H17/00; H03H17/02; (IPC1-7): G06G7/19
Domestic Patent References:
| JP3115427U |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)