Title:
SCALABLE OVERFLOW CLAMPING AND ITS METHOD FOR DIGITAL GAIN SCALER AND ADDER
Document Type and Number:
Japanese Patent JP3510142
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To keep the signal overflow at a fixed level and to minimize the oscillations of system output by clamping in a scalable way the positive or negative full scale signal of the 2nd addition node output so as to control the signal overflow at the allowable value in a system.
SOLUTION: A PDM(pulse density modulation) digital gain scaler/adder 20 uses the input gain registers 22, a 1st integrator 23, a 2nd integrator 31 and the addition nodes 24 and 32. Then the sealer/adder 20 mixes and scales plural single bit inputs received from every sigma-delta modulator by means of the output signal of a feedback gain register 26. A scalable overflow clamp 40 keeps the signal overflow capability of a fixed level for the composite single bit output that is generated from the mixing and scaling of those single bit inputs. Thus, it is possible to minimize the oscillations of the output of the scaler/adder 20 which are caused when the signal overflow is recovered.
Inventors:
Paul, Hendricks D.
Application Number:
JP9951299A
Publication Date:
March 22, 2004
Filing Date:
April 07, 1999
Export Citation:
Assignee:
LUCENT TECHNOL INC
International Classes:
H03M7/32; G06F7/60; H03M3/02; (IPC1-7): H03M7/32; H03M3/02
Attorney, Agent or Firm:
岡部 正夫 （外１０名）