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Title:
SCANNING SYSTEM FOR LOGICAL DEVICE
Document Type and Number:
Japanese Patent JPS6428744
Kind Code:
A
Abstract:

PURPOSE: To quickly and easily set and read the internal state by providing not only a means which scans FFs in a logical device with an address unique in the logical device but also a means which scans them with a common address.

CONSTITUTION: For example, plural channel devices 6 are provided in an input/ output processing device and the principal logic part of each device 6 is realized with an LSI. The scan address is set to an address register 11 in a scan control part 10. The set scan address is decoded by a decoder 12, which decodes scan addresses of individual devices 6, and a decoder 13 which decodes the scan address common to all devices 6. All devices are quickly initialized as block multiplexer channels by the output of the decoder 13, and a desired device 6 is quickly initialized as a byte multiplexer channel by the output of the decoder 12.


Inventors:
SATO HIROAKI
OKAMORI TOSHIYUKI
Application Number:
JP18331387A
Publication Date:
January 31, 1989
Filing Date:
July 24, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/22; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Katsuo Ogawa



 
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