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Title:
SCHOTTKY GATE FIELD-EFFECT TRANSISTOR
Document Type and Number:
Japanese Patent JPS63182867
Kind Code:
A
Abstract:

PURPOSE: To prevent occurrence of soft errors, by disposing a pair of Schottky gate electrodes which are configured at a specified distance apart from each other on a semiconductor substrate.

CONSTITUTION: A n-type impurity is selectively introduced on a surface of a semiconductor substrate 1 so as to form a n-type channel region 2, and next a WSix film 3 is formed. In succession an insulating film 4 is formed and then patterned. Thereafter, a WSix film 5 is formed and next the WSix films 5 and 3 are etched so that they remain on only side walls of the insulating film 4. In succession the WSix film 3 is etched. These remaining WSix films 5 and 3 compose Schottky gate electrodes G1 and G2. Namely, two Schottky gate electrodes G1 and G2 are formed at a specified distance apart from each other. Next, after the n-type impurity is implanted into the semiconductor substrate 1, an insulating film 6 such as a SiO2 film is formed, and then a n-type semicon ductor region 7, a source region 8, and a drain region 9 are self-formed by heat treatment.


Inventors:
KUROKAWA ATSUSHI
Application Number:
JP1404987A
Publication Date:
July 28, 1988
Filing Date:
January 26, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/28; H01L21/338; H01L27/10; H01L29/80; H01L29/812; (IPC1-7): H01L21/28; H01L27/10; H01L29/80
Attorney, Agent or Firm:
Katsuo Ogawa



 
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