PURPOSE: To improve the linearity of the Vg-Ids characteristic by a method wherein the high-density layer, the distance between the high-density layer and the gate electrode, and the intermediate density layer are formed in a specific relative relationship of the ratio of the length where the drain side end section of a channel depletion layer extends from the drain side end section of the gate electrode to the drain side to the gate length.
CONSTITUTION: A dummy gate 3 is formed on an active layer 2, and Si ions are implanted with the dummy gate 3 as a mask to form an n+ layer (high- density layer) 4. Si ions are implanted again with the contracted dummy gate 3a as a mask to form an n- layer 5 on an exposed active layer 2 section. A gate electrode 7 in schottky contact with the active layer 2 exposed from an inverted pattern. The n+ layer 4, the distance Lg-6+ between n+ layer 4 and gate electrode 7, and n- layer 5 are formed in a relative relationship where the ratio of the length L where drain side end section in the channel depletion layer extends from the drain side end section A of the gate electrode 7 to the drain side to the length Lg is in the range more than 1/5 and less than 1.
JPS63208275 | FIELD EFFECT TRANSISTOR |
JPH08316245 | SEMICONDUCTOR INTEGRATED CIRCUIT |
JP6007259 | Field effect transistor |
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