Title:
SCRAMBLER CIRCUIT
Document Type and Number:
Japanese Patent JPH04269035
Kind Code:
A
Abstract:
PURPOSE: To form a scramble circuit, which operates at a low line rate with a minimum electric power by executing a polynomial as a synchronous optical network(SONET) in parallel form added to SONET parallel data. CONSTITUTION: A timing window for making an FRMSYN signal high is a half cycle of DIV8 clocks on both the sides of the start of a new serial frame, and DIV8 is one eighth as large as a line rate. Then FRMSYN is synchronized with a descrambler by DIV8B with a clock. The FRMSYN is acquired by an FF which is clocked with DIV8B and then clocked in the FF with a high- speed clock, and its output becomes DSCREN. The DSCREN is applied to the set inputs of FFs 1 to 7 through a circuit, consisting of a multiplexer 144 and FFs 17 and 18. The FF 1 to FF 7 and an exclusive OR gate 110 execute SONET polynomial 1+X<6> +X<7> .
Inventors:
JIYON BII MAKUNESUBII
AMURITOPARU ESU KARA
ENJIERU RODORIKESU
AMURITOPARU ESU KARA
ENJIERU RODORIKESU
Application Number:
JP31426891A
Publication Date:
September 25, 1992
Filing Date:
November 28, 1991
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H04L25/03; H04L9/18; (IPC1-7): H04L9/18
Attorney, Agent or Firm:
Toshio Yano (1 outside)