Title:
SEMICODNUCTOR DEVICE, MEMORY CARD, AND DATA PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3883687
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent written data which are supplied externally to a data latch circuit from being lost by writing operation in order to write multi-level information in a memory cell.
SOLUTION: Written data externally given is latched by data latch circuits DLL, DLR, it is discriminated to which threshold value of multi-level the latched written data corresponds by each writing operation of plural stages, wiring control information being the discriminated result is latched to a sense latch circuit SL, and writing operation for setting threshold voltage of multi-level to a memory cell is performed stepwise according to the latched writing control information. Even if the writing operation is finished, the written data externally supplied at the beginning is left in the data latch circuit. Even if rewriting in a memory cell is performed caused by an over-writing state, it is not required to receive written data from the outside again.
Inventors:
Tetsuya Tsujikawa
Atsushi Nozoe
Mitsutaro Kanemitsu
Kubo Nozomi
Eiji Yamamoto
Ken Matsubara
Atsushi Nozoe
Mitsutaro Kanemitsu
Kubo Nozomi
Eiji Yamamoto
Ken Matsubara
Application Number:
JP3277698A
Publication Date:
February 21, 2007
Filing Date:
February 16, 1998
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/02; G11C11/56; G11C16/06; G11C16/10; (IPC1-7): G11C16/02
Domestic Patent References:
| JP10027486A | ||||
| JP9297996A |
Foreign References:
| WO1996024138A1 |
Attorney, Agent or Firm:
Shizuyo Tamamura
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