Title:
SEMICONDUCTOR ARITHMETIC CIRCUIT AND ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP3199707
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor arithmetic circuit capable of performing analog operation at high speed and for operating the absolute value of a difference in simple circuit configuration.
SOLUTION: Concerning the semiconductor arithmetic circuit for operating the absolute voltage of a difference between a first signal voltage VM and a second signal voltage VX, this circuit is provided with first and second MOS transistors 101 and 102 connecting source electrodes having floating gates 103 and 104 and control gates 116 and 117 of capacitive coupling, a write circuit for setting the potential of the floating gate 103 to VM and setting the potential of the floating gate 104 to VDD-VM in the state of impressing a prescribed voltage to the control gates of the first and second MOS transistors and a differential voltage operating circuit for operating VDD-VX, VDD-VX is impressed to the control gate 116 of the first MOS transistor and VX is impressed to the control gate 117 of the second MOS transistor.
Inventors:
Naoshi Shibata
Masahiro Honda
Tadahiro Ohmi
Masahiro Honda
Tadahiro Ohmi
Application Number:
JP22558199A
Publication Date:
August 20, 2001
Filing Date:
August 09, 1999
Export Citation:
Assignee:
Semiconductor Science and Engineering Research Center Co., Ltd.
International Classes:
G06G7/12; G06G7/14; (IPC1-7): G06G7/14
Attorney, Agent or Firm:
Takashi Ishida (4 others)