Title:
SEMICONDUCTOR CHIP, MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR MODULE, AND ELECTRONIC APPARATUS
Document Type and Number:
Japanese Patent JP3858545
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent a signal from being delayed by directly connecting a laminated semiconductor chip, without use of a wire for shorter conductive path.
SOLUTION: After an electrode 16 is formed on a chip body surface 14, a vertical hole 24 is dug from a backside 22 of the chip body, until the electrode 16 is exposed. A metal wiring 30 is led out of a tungsten 18 and exposed in the vertical hole 24 to the backside 22 of chip main body. With this configuration for the semiconductor chip, the metal wiring 30 is drawn out, with the shortest distance from the surface 14, where the electrode 16 is formed to the backside 22 via the vertical hole 24. Other semiconductor chip, etc., is connected to the metal wiring 30 for the shortest connection to the electrode 16, so as to prevent a signal from being delayed.
Inventors:
Hidekazu Sato
Application Number:
JP37118899A
Publication Date:
December 13, 2006
Filing Date:
December 27, 1999
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L23/52; H01L25/18; H01L21/3205; H01L25/065; H01L25/07; (IPC1-7): H01L25/065; H01L25/07; H01L25/18; H01L21/3205
Domestic Patent References:
| JP1108730A | ||||
| JP1129441A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa
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