Title:
SEMICONDUCTOR CHIP, WIRING BOARD AND THEIR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3433193
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor chip, its manufacturing method and a semiconductor device in which the thickness of the semiconductor device, the area of a substrate or the wiring length between semiconductor chips is not increased even if a plurality of semiconductor chips are placed, in layers, on a wiring board.
SOLUTION: The semiconductor chip comprises a semiconductor substrate 13, a first external electrode 21 formed on the first surface 14 of the semiconductor substrate 13, a second external electrode 22 formed on the second surface 17 of the semiconductor substrate 13, and a through hole 16 made through the semiconductor substrate 13. The through hole 16 is made in an inclining face 15 formed to have an obtuse internal angle with respect to the second surface 17 and the first external electrode 21 is connected electrically with the second external electrode 22 through a conductive pattern 19 formed via the inner wall of the through hole 16 and the inclining face 15.
Inventors:
Yuichiro Yamada
Application Number:
JP2001233962A
Publication Date:
August 04, 2003
Filing Date:
August 01, 2001
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L23/52; H01L21/3205; H01L21/768; H01L23/12; H01L25/065; H01L25/07; H01L25/18; (IPC1-7): H01L23/12; H01L23/52; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| JP8264712A | ||||
| JP575014A |
Other References:
【文献】国際公開99/010925(WO,A1)
Attorney, Agent or Firm:
Akio Miyai