Title:
半導体回路
Document Type and Number:
Japanese Patent JP3611340
Kind Code:
B2
Abstract:
PCT No. PCT/JP94/02258 Sec. 371 Date Jun. 28, 1996 Sec. 102(e) Date Jun. 28, 1996 PCT Filed Dec. 27, 1994 PCT Pub. No. WO95/18488 PCT Pub. Date Jul. 6, 1995A simple semiconductor circuit by which analog data or multilevel data can be fetched and stored. The circuit receives a first signal and converts the first signal into a second signal composed of multilevel. The second signal is fed back to the circuit. The circuit is constituted of a first circuit which converts the first signal into a signal group composed of multiple quantized signals and second circuit which converts the signal group into the second signal. In addition, the first or/and second circuits are constituted of one or more neuron MOS transistors.
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Inventors:
Nao Shibata
Takeo Yamashita
Tadahiro Ohmi
Takeo Yamashita
Tadahiro Ohmi
Application Number:
JP35208693A
Publication Date:
January 19, 2005
Filing Date:
December 28, 1993
Export Citation:
Assignee:
Nao Shibata
UCT Co., Ltd.
I & F Co., Ltd.
Tadahiro Ohmi
UCT Co., Ltd.
I & F Co., Ltd.
Tadahiro Ohmi
International Classes:
G06F3/05; G06F15/18; G06G7/60; G06N3/06; G06N3/063; G11C27/00; H01L21/8234; H01L27/088; H03K3/3568; H03K19/20; H03M1/12; H03M1/36; H03M1/80; (IPC1-7): G06N3/063; H03K19/20; H03M1/36
Domestic Patent References:
| JP61133718A |
Foreign References:
| WO1992016971A1 |
Other References:
Shibata, T., et.al.,"A functional MOS transistor featuring gate-level weighted sum and threshold operations",IEEE Transactions on Electron Devices,1992年 6月,Vol.39, No.6,pp.1444-1455,ISSN:0018-9383
Attorney, Agent or Firm:
Hisao Fukumori