Title:
SEMICONDUCTOR DEVICE AND ARITHMETIC OPERATION SYSTEM USING THE SAME, IMAGE PROCESSING SYSTEM, SOUND SIGNAL PROCESSING SYSTEM, PATTERN RECOGNITION SYSTEM, SIGNAL PROCESSING SYSTEM, PARALLEL DATA PROCESSING SYSTEM, AND VIDEO SIGNAL PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP3512292
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To constitute a large-scale highly parallel system, having operation elements coupled closely with one another, in one chip by using a device which has a floating node.
SOLUTION: Capacity means 8-13 are connected to input terminals 16-21 respectively. The common connection part between the uninverted input terminal 6 of a high-input-impedance operational amplifier 1 and capacity means 8-11, and the contact of the common connection part between the inverted input terminal 7 and capacity means 12-15 are floating nodes respectively. This arithmetic circuit comes into a signal operation mode wherein the signal from a precedent-stage operational amplifier 23 is received and processed when a reset signal 5 is negative. The gain setting of the operational amplifier 1 is determined by the capacity ratio of a capacity means 15 for negative feedback, and a grounded capacity means 14 and capacity means 8-13. By changing the capacity ratio, multi-valued linear operation is made possible.
Inventors:
Omi, Tadahiro
Ogawa, Katsuhisa
Ogawa, Katsuhisa
Application Number:
JP1396196A
Publication Date:
March 29, 2004
Filing Date:
January 30, 1996
Export Citation:
Assignee:
Omi, Tadahiro
CANON INC
CANON INC
International Classes:
G06F7/501; G06G7/14; G06J1/00; H03F3/70; H03H19/00; H03M1/80; (IPC1-7): G06G7/14; G06F7/50
Attorney, Agent or Firm:
山下 穣平
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