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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND ASSEMBLING METHOD THEREOF
Document Type and Number:
Japanese Patent JPH0521691
Kind Code:
A
Abstract:

PURPOSE: To enable a common electric path such as a power supply or the like to be lessened in resistance by a method wherein a second lead is arranged in parallel with one of the sides of a semiconductor chip, and the lead is connected to a pad through the intermediary of a wire.

CONSTITUTION: In a lead frame 100, grounding inner leads 23, 29, and 39 are connected in one piece as shown by slant lines. All inner leads 25, 27, 31, 33, 35, and 37 used as grounding inner leads can be disused, so that the space where inner leads were is to be open. Inner leads used in common are made to extend along the end of a region where inner leads 30-38 are connected to the pads of an IC chip 51 and apart from it by a prescribed distance, the end of this inner lead is formed into one piece with a GND inner lead 29 on an arrangement first stage side, and the other end of the lead is formed into one piece with a GND inner lead 39 on an arrangement final stage side. The inner lead can be connected to a pad with a wire or the like, they can be connected to each other at the shortest distance.


Inventors:
HIRASHIMA TOSHINORI
Application Number:
JP32197791A
Publication Date:
January 29, 1993
Filing Date:
December 05, 1991
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L23/50; (IPC1-7): H01L23/50
Domestic Patent References:
JP46011609A
JPS5394875A1978-08-19
Attorney, Agent or Firm:
Akita Aki