To enhance a main of a step/hold period of time by a method wherein a plurality of input buffers for receiving each of external signals in synchronism with a clock signal are arrayed adjacent to each other in no relation to an array gap of input/output pads.

A semiconductor device contains five input/output pads 10, 12, 14, 16, 18; five data output buffers 20, 22, 24, 26, 28; and five data input buffers 30, 32, 34, 36, 38. In this semiconductor memory device, input buffers 30 to 38 for receiving each of external signals in synchronism with a clock signal are arrayed adjacent to each other in no relation to an array gap of corresponding input/output buffer pads 10 to 18. Accordingly, a skew of a single for the input buffers 30 to 38 such as a control signal, a clock signal, or the like is minimized. As the results, a margin of a setup/hold period of time of input data is enhanced and control of the input buffers 30 to 38 is facilitated.