Title:
SEMICONDUCTOR DEVICE AND DISPLAY UNIT
Document Type and Number:
Japanese Patent JP3276900
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the occupation ratio of an imperfect region with respect to the channel width, and restrain the deterioration of element characteristics by making the summed distance of each channel width in a plurality of channel regions and the isolation distance larger than the pitch of a pulsed laser.
SOLUTION: An defective crystallization region R is generated in the same position as in conventional case. The right channel region CH is covered with the region R. The left channel region CH is isolated from the region R. In an element, a moving path Mg having a width W2 in the total width W of the channel becomes practically satisfactory. When the defective crystallization region R having a width P is generated passing the region of an FET, the region R does not occupy the whole width of the channel region CH. Thereby satisfactory element characteristics can be obtained, in virtue of the moving path MG formed in the channel region CH outside the defective crystallization region R.
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Inventors:
Yasuo Segawa
Tsutomu Yamada
Ryoichi Yokoyama
Kiyoshi Yoneda
Tsutomu Yamada
Ryoichi Yokoyama
Kiyoshi Yoneda
Application Number:
JP26667997A
Publication Date:
April 22, 2002
Filing Date:
September 30, 1997
Export Citation:
Assignee:
Sanyo Electric Co., Ltd.
International Classes:
G02F1/1345; G02F1/136; G02F1/1368; G09F9/33; H01L21/02; H01L21/20; H01L21/336; H01L27/12; H01L29/786; (IPC1-7): H01L21/336; G02F1/1368; G09F9/33; H01L21/20; H01L29/786
Domestic Patent References:
| JP974205A | ||||
| JP58178565A |
Attorney, Agent or Firm:
Masamasa Shibano