Title:
SEMICONDUCTOR DEVICE HAVING INCORPORATED P-TYPE AND N-TYPE IMPURITY INDUCTIVE LAYER NON-ORDERED MATERIAL
Document Type and Number:
Japanese Patent JPH07221409
Kind Code:
A
Abstract:
PURPOSE: To provide a semiconductor device which has selected regions of an n-type and a p-type material of a wide band gap by forming n-type and p-type regions by impurity induction layer disordering. CONSTITUTION: On a GaAs semiinsulating substrate 110, a P-Ga1-x Alx As clad layer 114 is epitaxially deposited. Then, on the clad layer 114, an active P-type multilayer 116 which serves as an active waveguide section 121 in a laser section and serves as a base channel 123 in a transistor section and a P-Ga1-x Alx As clad layer 120 are deposited in order. Then, this device 100 of a heterostructure is annealed to deposite a silicon layer which is rich in arsenic and potassium. Then, silicon atoms of the silicon layer are diffused into the multilayer 114 or 120 of a heterostructure and thereby silicon impurity induction disordering regions 130, 132 and 140 are formed. The disordering region 132 separates a base contact 128 from the active waveguide section 121.
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Inventors:
TOOMASU ERU PAORII
JIYON II NOOSURATSUPU
JIYON II NOOSURATSUPU
Application Number:
JP31742594A
Publication Date:
August 18, 1995
Filing Date:
December 21, 1994
Export Citation:
Assignee:
XEROX CORP
International Classes:
H01L29/73; H01L21/331; H01L27/06; H01L27/15; H01L29/205; H01L29/737; H01S5/00; H01S5/026; H01S5/042; H01S5/20; H01S5/12; H01S5/183; (IPC1-7): H01S3/18; H01L21/331; H01L29/205; H01L29/73
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)