Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JPH10270568
Kind Code:
A
Abstract:

To improve the characteristic of a MOS transistor in a peripheral circuit area, by forming the first source/drain areas of a memory circuit area with a single area, and providing a first metallic silicide layer on the surface of the second source/drain areas of the peripheral circuit area.

First source/drain areas 6 and 7 of a first MOS transistor in the memory circuit area are formed by the single impurity area. First metallic silicide layers 21a and 21b are provided for second source/drain areas 22a and 22b of the second MOS transistor in the peripheral circuit area. Since the metallic silicide layer is not formed in the first/drain areas 6 and 7, the deterioration of the characteristic of the memory circuit owing to the occurrence of a crystal defect and the occurrence of junction leak can be avoided. The wiring resistance of the second source/drain areas 22a and 22b can be reduced and junction capacity can be reduced.


Inventors:
SHIRATAKE SHIGERU
Application Number:
JP7164597A
Publication Date:
October 09, 1998
Filing Date:
March 25, 1997
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/8238; H01L21/8234; H01L27/092; H01L27/105; (IPC1-7): H01L21/8238; H01L27/092
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)



 
Previous Patent: TRANSISTOR PROTECTIVE ELEMENT

Next Patent: CLAMPING CIRCUIT