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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2005183923
Kind Code:
A
Abstract:

To downsize a semiconductor device where a plurality of semiconductor elements are laminated.

A first semiconductor element 3 and a second semiconductor element 8 are adhered with a die bonding material 7, and an electrode 6a of the first semiconductor element 3 and a first bonding layer are joined by flip-chip bonding on a semiconductor carrier 1 which has the bonding layer 2 on one surface and a second bonding layer 12 on the surrounding portion of the other surface, and a bonding pad 9 of the second semiconductor element 8 and the second bonding layer 12 of the semiconductor carrier 1 are connected with a metal thin wire 10 by wire bonding, and the surrounding of the first semiconductor element between the semiconductor carrier 1 and the second semiconductor element 8 and the wire bonding portion are filled with an insulating sealing resin 13, and the sealing filled area 20 is formed in almost the same external form dimension to the second semiconductor element 8.


Inventors:
FUJITANI NAOKI
AKABOSHI TOSHITAKA
ITO FUMITO
FUKUDA TOSHIYUKI
Application Number:
JP2004197483A
Publication Date:
July 07, 2005
Filing Date:
July 05, 2004
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L23/00; H01L23/12; H01L25/04; H01L25/065; H01L25/18; H01L25/07; H01L27/108; (IPC1-7): H01L25/065; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Takao Itagaki
Yoshihiro Morimoto
Toshiji Sasahara
Yohei Harada