To provide a semiconductor device in which an SOG film is utilized for relaxing the irregularity of an interlayer insulating film and reliable circuit wiring is attained even if holes are formed in extremely close proximity, and to provide its manufacturing method.
A superficial clearance D1 between a contact hole 12 and a via hole 15 is set at 1 μm or less as a minimum space. A dummy pattern 18 is formed of a first layer metal wiring layer along the boundary of a memory cell region contiguous to a peripheral circuit region. At the time of applying an SOG film, the dummy pattern 18 blocks undue movement to the memory cell region side caused by film fluidity. Consequently, the SOG film remains constantly in the memory cell region and at the outermost circumference when it is applied to a memory cell region of dense irregularity.
Masaaki Utsunomiya
Atsushi Watanabe