Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP3448023
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To avoid exposing electrodes or wirings underlying an interlayer dielectric film, even with a reduced thickness of the interlayer dielectric deposited on the lower side of a laminate film including a ferroelectric film.
SOLUTION: After depositing a first silicon oxide film 103 containing boron and phosphorus on a semiconductor substrate 100 with a wiring 101 through a silicon nitride film 102, the silicon oxide film 103 is planarized. After wet etching this film 103 to reduce its thickness, a second silicon oxide film 105 not containing such an impurity as boron or phosphorus is deposited on the oxide film 103. After depositing a first metal film 106, ferroelectric film 107 and second metal film 108 on the oxide film 105, they are patterned one after another to form capacitor elements composed of upper electrodes 108A, capacitive insulating film 107A and lower electrodes 106A. Other regions of the oxide film 105 where no capacitor element is formed are removed by wet etching.
Inventors:
Toyoji Ito
Application Number:
JP2000306032A
Publication Date:
September 16, 2003
Filing Date:
October 05, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L23/522; H01L21/768; H01L21/8246; H01L27/105; (IPC1-7): H01L27/105; H01L21/768
Domestic Patent References:
| JP200068463A | ||||
| JP2000150868A | ||||
| JP1167910A | ||||
| JP11340433A | ||||
| JP11340317A |
Attorney, Agent or Firm:
Hiroshi Maeda (7 outside)
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