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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JPS5534488
Kind Code:
A
Abstract:

PURPOSE: To heighten the integration density by making multi-crystalized semiconductor layer into three dimention structure with electrode wiring layer, thru the method wherein the process of growing single crystal semiconductor and the process of forming multi-crystal semiconductor layer among the former semiconductor layers are repeated.

CONSTITUTION: Oxide membrane 2 is left in stripe form on a p-type crystal semiconductor substrate 1, while an n-type single crystal silicon layer 3 of high density is epitaxial grown and are made as IGFET source. Oxide membrane 4 is thickly formed covering whole surface, multi-crystal Si layer 5 is laminated at gate position, which is polish finished until the polishing reaches the upper surface of oxide membrane 4 and is etched selectively. By repeating the above procedures, single crystal Si layers 3,6,9 are made into source channel drain region, and IGFET is constructed three dimentionally wherein thin oxide membranes 7 are made into gate insulation membranes and multi-crystal Si layer 8 are made into gate electrodes.


Inventors:
HIRASHIMA KUNIHIKO
Application Number:
JP10787278A
Publication Date:
March 11, 1980
Filing Date:
September 01, 1978
Export Citation:
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Assignee:
PIONEER ELECTRONIC CORP
International Classes:
G11C11/412; H01L21/3205; H01L21/822; H01L21/8244; H01L23/52; H01L27/00; H01L27/04; H01L27/06; H01L27/11; H01L29/78; H01L29/786; (IPC1-7): H01L21/74; H01L21/88; H01L27/04; H01L29/78