To provide a semiconductor device chip size of which is reduced and the cost of which is decreased.
The semiconductor device is provided with a memory cell array 11, word lines WL1 to WLn; and a decode circuit 14. The decode circuit 14 includes reading decoders 12-1 to 12-n provided corresponding to the word lines and decoding an address signal to select each word line; and high withstanding voltage transistors QA1 to QAn the one-side ends of respective current paths of which are connected to output terminals of the reading decoders, and the other-side ends of which are connected to one-side ends of the word lines. The same number of the high withstanding voltage transistors as the number of the word lines is arranged, and each of the high withstanding voltage transistors is arranged along the extension direction of each of the word lines. Each gate electrode is arranged in a direction orthogonal to the extension directions of the word lines, and the high withstanding voltage transistors are subjected to ON/OFF control with a control signal SA.
HIRATA YOSHIHARU
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Sadao Muramatsu
Ryo Hashimoto