Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3268158
Kind Code:
B2
Abstract:
PURPOSE: To give a potential to a buried wiring layer small in area occupied by it by a method wherein a second conductivity-type wiring layer which leads out a semiconductor region up to the surface of a substrate is provided around a second trench.
CONSTITUTION: An N-type diffusion layer 17 reaching the surface of a substrate 1 is formed to function as a leading wiring layer which leads out a buried wiring layer 15 to the surface of the substrate 1. Contact holes are provided in an oxide film 27 adjacent to a leading trench 3A. The surface of the N-type diffusion layer 17 is exposed out of the oxide film 27 in each of the contact holes. By this setup, the buried wiring layer 15 is led up to the surface of the substrate 1. A plate potential power supply wire 37 is formed on the oxide film 27. The plate potential power supply wire 37 is electrically connected to the N-type diffusion layer 17 through the intermediary of the contact holes, whereby a plate potential VPL is supplied to the buried wiring layer 15 through the intermediary of a lead-out wiring layer formed along the side wall of a trench 3A. The plate potential power supply wiring 37 is formed of the same conductive polysilicon with, for instance, a wiring layer 33.
Inventors:
Atsuko Takahashi
Yuusuke Kouyama
Yuusuke Kouyama
Application Number:
JP7675895A
Publication Date:
March 25, 2002
Filing Date:
March 31, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/318; H01L21/76; H01L21/8242; H01L27/108; H01L29/94; H01L27/105; (IPC1-7): H01L21/8242; H01L21/76; H01L21/822; H01L27/04; H01L27/108
Domestic Patent References:
| JP63136559A | ||||
| JP563155A |
Attorney, Agent or Firm:
Takehiko Suzue
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