PURPOSE: To provide each element isolation groove which is equipped with sufficient breakdown strength and is finished with fine dimensions by making sidewalls of the isolation groove made in the direction of width have slanting faces and the sidewalls of the groove made in the direction of length have almost vertical faces in a channel region when a MOS transistor is integrated.

CONSTITUTION: An SiO2 mask 21 is applied on a p-type Si substrate 1 and CF3Br is used as an etching gas and then, an ultraviolet light beam radiated by eximer laser is irradiated. When its beam in the channel width direction is irradiated only in the vertical direction and the beam in the channel length direction is irradiated while swinging its beam, the groove 2a having vertical walls and the groove 2b having slanting walls are formed. Deposited substances 22 are removed by burning them in O2 plasma. The inversion is prevented by providing a B ion implantation layer 24. A CVD SiO2 film 3 is deposited and it is left only in the isolation groove 2 by RIE. Further, B ions are activated by heat treatment and a p-type layer 4 is formed as a channel stopper. After that, element formation is performed and, while making element characteristics optimum after selecting the form the element isolation groove by its direction, the fineness and high integration of a device is realized only by setting etching conditions.