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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH04318937
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of vertical wall-shaped residue at a time when plasma etching is conducted by isotropic-etching a first insulating layer formed onto a conductive layer, forming a second insulating layer onto the first insulating layer and anisotropic-etching the second insulating layer.

CONSTITUTION: A gate insulating film 2 is formed onto a semiconductor substrate 1. A polysilicon film is formed, an insulating film 4 is shaped, and a resist 5 is formed in a specified region on the insulating film 4. The insulating film 4 is isotrpic-etched until the film pressure of the insulating film 4 reaches one fifth or a half, and the residual section of the insulating film 4 is anisotropic-etched. The resist 5 is removed, and the polysilicon film 3 is anisotropic-etched. Impurity ions are implanted to the semiconductor substrate 1. An insulating film 6 is formed on the whole surface. Sidewalls 6a are formed. Impurity ions are implanted to the semiconductor substrate 1. A resist 8 is shaped onto a polysilicon film 7. The polysilicon film 7 is anisotropic-etched. The resist 8 is removed, and insulating films 51, 52 are formed.


Inventors:
HOSHIKO TAKAHIRO
OGAWA TOSHIAKI
Application Number:
JP8548791A
Publication Date:
November 10, 1992
Filing Date:
April 17, 1991
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H01L21/265; H01L21/033; H01L21/266; H01L21/28; H01L21/302; H01L21/3065; H01L21/336; H01L21/768; H01L29/78; (IPC1-7): H01L21/265; H01L21/302; H01L21/336; H01L29/784
Domestic Patent References:
JPH02211633A1990-08-22
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)



 
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