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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH07142576
Kind Code:
A
Abstract:

PURPOSE: To eliminate error connection between both wirings and the generation of defective connection by forming a column-like contact part in a lower layer wiring at the time of forming a lower layer pattern to prevent positional displacement and a contact resistance defect between the lower layer wiring and the contact part.

CONSTITUTION: An intermediate aluminum in which a first wiring 2, an etching stopper 3 and a contact part 4 are formed is bonded to cover a wafer 1. Etching is performed by using a resist pattern 5 to form a first layer aluminum layer to intermediate aluminum layer in accordance with the patterns of the first layer wiring. Next, the resist pattern 5 is removed, and a resist 6 is applied thereto again, and a resist on non-contact part is removed. At that time, adequate margin 14 is taken. Only non-contact part 13 is removed to form a column-like part to make the contact part 4 on the first layer wiring 2. Next, an oxide film 7 is deposited and then flattening is performed until the contact part 4 is exposed. Thereby, an upper and a lower layer wiring can be surely interconnected.


Inventors:
MORINAGA SHIRO
Application Number:
JP28927493A
Publication Date:
June 02, 1995
Filing Date:
November 18, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/52; H01L21/3205; H01L21/768; (IPC1-7): H01L21/768; H01L21/3205
Domestic Patent References:
JPS61208850A1986-09-17
JPS62291138A1987-12-17
JPS612346A1986-01-08
Attorney, Agent or Firm:
Wakabayashi Tadashi