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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH09246490
Kind Code:
A
Abstract:

To inhibit the formation of a resistance layer or the like on the interface between an electrode and a dielectric film consisting of a metallic oxide film.

Two element isolation oxide films 2 are formed mn parts of the upper part of a P-type substrate. 1 and N+ diffused layers 3a and 3b are formed in such a way that they are held between the two element isolation oxide films 2. A gate electrode 5 covered with a gate insulating film 4 is formed on the substrate 1 in such a way that it bridges the layers 3a and 3b. An interlayer insulating film 6a is formed on the film 4 and the substrate 1. A bit line 7 connected with the layer 3a is formed on the film 6a. An interlayer insulaitng film 6b is formed on the film 6a and the bit line 7. An Ru film 10 is formed on a polycrystalline silicon film 8 on the layer 3b via a TiN film 9. An SrRuO3 film 11 is formed in such a way as to cover the film 10, an SrTiO3 film 12 is formed on the film 11 and an Ni film 13 is formed on one part of the film 12.


Inventors:
MOTAI TAKAKO
IMAI KEITAROU
Application Number:
JP5321996A
Publication Date:
September 19, 1997
Filing Date:
March 11, 1996
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L21/8246; H01L27/105; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242; H01L27/04; H01L21/822
Attorney, Agent or Firm:
Takehiko Suzue