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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS61104665
Kind Code:
A
Abstract:

PURPOSE: To contrive to improve the coverage characteristic of a gate insulation film at the edge of a gate metallic layer, by a method wherein the side wall is formed in the side of a gate out of the first insulation layer, and the gate metal is embedded after the second insulation layer is lifted off.

CONSTITUTION: A gate metal 2 and a lift-off layer 13 are formed on an insulation substrate 1, and the first insulation layer 14 is formed by a coat of oxide Si; thereafter, the side wall 14' is formed in the side of the gate metallic layer 2 by etching. Next, the second insulation layer 15 is adhered to almost the same film thickness as that of the metal layer 2. This insulation layer formed by plasma discharge is generally weak in chemical bond at the step: when this layer is kept dipped in etchant, the edge of the step extinguishes and the base is exposed. Then, the second insulation layer 15 on the lift-off layer 13 is removed by melting away the side-exposed lift-off layer 13 through dipping in a solution of nitride acid, resulting in the formation of the gate metallic layer 2 exposed flatly. Thereafter, the MIS transistor completes through the same process as the conventional.


Inventors:
SAITO HIROKI
KAWASAKI KIYOHIRO
Application Number:
JP22569584A
Publication Date:
May 22, 1986
Filing Date:
October 29, 1984
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/336; H01L27/12; H01L29/78; H01L29/786; (IPC1-7): H01L27/12
Attorney, Agent or Firm:
Hiroshi Matsumura (2 outside)



 
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