Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR AS WELL AS METHOD FOR FORMING MASK PATTERN
Document Type and Number:
Japanese Patent JP2001230250
Kind Code:
A
Abstract:
To apply an OPC to a large scale logic circuit by reducing a DA treating time in the case of OPC treating a random pattern such as the logic circuit or the like.
A dummy pattern 16 is disposed on a periphery of a wiring 15 having an isolated patterning (e.g. a penetrating through hole pattern). In the case of applying the OPC to the penetrating through hole part or a line end of the wiring 15, a predetermined rule is applied without considering the state of a peripheral pattern, and a hammer head 17 is added.
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Inventors:
HOTTA SHOJI
FUKUDA HIROSHI
AOKI HIDEO
MORI KAZUTAKA
HASEGAWA NORIO
FUKUDA HIROSHI
AOKI HIDEO
MORI KAZUTAKA
HASEGAWA NORIO
Application Number:
JP2000035297A
Publication Date:
August 24, 2001
Filing Date:
February 14, 2000
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H01L21/3205; G03F1/36; G03F1/68; G03F1/70; H01L21/768; H01L21/82; H01L21/8238; H01L23/52; H01L23/522; H01L27/092; (IPC1-7): H01L21/3205; H01L21/82; H01L21/8238; H01L27/092
Domestic Patent References:
| JPH11297817A | 1999-10-29 | |||
| JPH1032253A | 1998-02-03 | |||
| JPH11174658A | 1999-07-02 |
Attorney, Agent or Firm:
Yamato Tsutsui