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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
Japanese Patent JP2013153040
Kind Code:
A
Abstract:

To provide a semiconductor device manufacturing method capable of precisely forming a two-stage LLD structure.

The method has the steps of: injecting impurity ions to a semiconductor layer 30a using a gate electrode 30g as a mask; forming a first resist pattern 41 planarly overlaid on a first region 41a adjacent to the gate electrode 30g and both ends of a channel region 30c in a channel longitudinal direction; injecting the impurity ions to the semiconductor layer 30a using the first resist pattern 41 as a mask; forming a second resist pattern 42 planarly overlaid on a second region 42a adjacent to a side of at least a single side of the first region 41 opposite to the channel region 30c; injecting the impurity ions to the semiconductor layer 30a using the first resist pattern 41 and the second resist pattern 42 as masks; and removing the first resist pattern 41 and the second resist pattern 42.


Inventors:
NAKAJIMA HISAAKI
IIZUKA SHOTA
Application Number:
JP2012012754A
Publication Date:
August 08, 2013
Filing Date:
January 25, 2012
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H01L21/336; G02F1/1368; H01L29/786
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Kazuhiko Miyasaka