Title:
SEMICONDUCTOR DEVICE AND MEMORY CELL CIRCUIT
Document Type and Number:
Japanese Patent JP2023040898
Kind Code:
A
Abstract:
To suppress power consumption in a semiconductor device including a memory cell and a non-volatile storage part.SOLUTION: A semiconductor device includes: a memory cell which holds 1-bit data; a pair of bit lines for writing or reading data into or from the memory cell; a non-volatile storage part which stores the data held by the memory cell; and a writing control part which causes the data currently held by the memory cell to be stored in a first storage part, causes the data currently stored in the non-volatile storage part to be stored in a second storage part, and when the data stored in the first storage part and the data stored in the second storage part differ from each other, causes the data stored in the first storage part to be written into the non-volatile storage part via the pair of bit lines and, when the data stored in the first storage part and the data stored in the second storage part are identical to each other, causes the data stored in the first storage part not to be written into the non-volatile storage part.SELECTED DRAWING: Figure 3
Inventors:
USAMI MASAYOSHI
Application Number:
JP2021148090A
Publication Date:
March 23, 2023
Filing Date:
September 10, 2021
Export Citation:
Assignee:
SHIBAURA INST TECH
International Classes:
G11C14/00; G11C11/16
Attorney, Agent or Firm:
Patent Attorney Corporation Taiyo International Patent Office
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