To cut down the number of the PEP processes to enable reduction of the manufacturing cost by implementing field implantation and channel implantation successively making use of the same mask for ion implantation.
Shallow trench isolations STIs 21 of a trench-embedded structure are formed in a semiconductor layer 20, and MOS element regions 22 formed of the semiconductor layer 20 surrounded by the STIs 21 are formed. A mask layer 25 having open portions 26 is formed on the semiconductor layer 20, each open portion 26 extending continuously over the entire area of each MOS element region 22 and the areas that partly cover the STIs 21 provided around the MOS element region of interest. First impurity ions are implanted onto the entire surface by way of the mask layer 25 such that the peak of the profile of the impurity ions is located in the semiconductor layer 20 directly below the bottom surface of the STI 21. Second impurity ions are implanted onto the entire surface by way of the mask layer 25 such that the peak of the profile of the impurity ions is located in the middle in the direction of the depth of the STI 21. The first and second impurity ions are activated.
NAKANO TAKESHI
UENO HIROTAKA
SHIMIZU AKIRA
TOSHIBA MICRO ELECTRONICS
Satoshi Kono
Makoto Nakamura
Sadao Muramatsu
Ryo Hashimoto
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