To provide a method for manufacturing a semiconductor device that prevents dispersion in gate electrode shapes between a p-MOS transistor and an n-MOS transistor and is suitable for fining.

The system has a process for forming the gate electrode where a dopant concentration in an upper portion interposed by a gate insulating film on the principal surface of a semiconductor substrate 11 is higher than that in a lower portion and conductive types in first and second regions are different from each other, a process for forming upper portions 18a, 23a of first and second gate electrodes by etching the upper portions of the gate electrode films in the first and the second regions with a first insulating film having a gate electrode pattern as a mask, a process for forming a second insulating film on the sidewalls of the upper portions 18a, 23a of the first and the second gate electrodes, and a process for forming lower portions 18b, 23b of the first and the second gate electrodes by etching the lower portion of the gate electrode in the first and the second regions.