Title:
半導体装置、半導体装置の製造方法
Document Type and Number:
Japanese Patent JP7188643
Kind Code:
B2
Abstract:
A semiconductor device includes a multi-layer board which a wiring pattern and a grounding pattern are formed. A plurality of semiconductor elements are mounted on the multi-layer board. An insulating sealing member is provided on the multi-layer board and is covering the plurality of semiconductor elements. A metal film is provided on the insulating sealing member. An in-groove metal is provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board. An in-hole metal is provided in an inner wall of a hole penetrating through the insulating sealing member and is extending to the multi-layer board. The in-hole metal is contacting with the metal film and the grounding pattern.
Inventors:
Yoshihiro Tsukahara
Minoru Kimura
Minoru Kimura
Application Number:
JP2022524857A
Publication Date:
December 13, 2022
Filing Date:
May 22, 2020
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L23/00; H01L23/28; H05K3/28; H05K3/46; H05K9/00
Domestic Patent References:
| JP2017191835A | ||||
| JP2019117866A | ||||
| JP2012039104A |
Foreign References:
| WO2015194435A1 | ||||
| US20100109132 |
Attorney, Agent or Firm:
Patent Attorney Takada / Takahashi International Patent Office