To provide a semiconductor device which makes it possible to properly review wafer test conditions in a short time.

In a variable resistance circuit 32 included in an internal source potential generating circuit 1 of a DRAM, an N channel MOS transistor 47 is connected to fuses 48 to 51 for tuning an internal source potential intVCC in parallel. In LT previous-state return mode, a signal LTB goes up to 'H' level and the N channel MOS transistor 47 turns on; and then the same state as a state wherein none of the fuses 48 to 51 is cut is entered and the internal source potential intVCC returns to the level at wafer test time. After a final test, the wafer conditions can, therefore, be reviewed.