Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3719650
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enhance noise resistance of a semiconductor device which has a dummy diffusion layer formed on a substrate.
SOLUTION: Between an analog block 50 and a digital block 51, a dummy diffusion layer 11 is formed as countermeasures against dishing in CMP of STI process. The surface of the dummy diffusion layer 11 is covered with a dummy gate electrode 13 and protected against silicification. Since formation of the dummy gate electrode 13 can be executed, in combination with ordinary formation of the gate electrode of a transistor, and no fabrication process needs to be added newly.
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Inventors:
Satoshi Ishikura
Yukio Iijima
Nobuaki Mizuguchi
Yukio Iijima
Nobuaki Mizuguchi
Application Number:
JP2000389753A
Publication Date:
November 24, 2005
Filing Date:
December 22, 2000
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/76; H01L21/761; H01L21/762; H01L21/822; H01L21/8238; H01L27/04; H01L27/08; H01L27/092; (IPC1-7): H01L21/76; H01L27/08
Domestic Patent References:
| JP10154751A | ||||
| JP2002076111A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Teshima Masaru
Atsushi Fujita
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