Title:
半導体装置
Document Type and Number:
Japanese Patent JP4822292
Kind Code:
B2
Abstract:
The semiconductor device includes a P-type semiconductor region and an MOS transistor. MOS transistor includes a gate electrode, a collector electrode, a drain electrode, an N-type impurity region and a P-type impurity region. N-type impurity region is electrically connected to the drain electrode. P-type impurity region is electrically connected to the collector electrode. P-type impurity region is electrically connected to the drain electrode. The semiconductor device further includes an N-type impurity region and an electrode. N-type impurity region is electrically connected to the gate electrode. The electrode is formed on the P-type semiconductor region with an insulating film therebetween, and is electrically connected to gate electrode. Thereby, an element footprint can be reduced while maintaining characteristics.
Inventors:
Tomohide Terashima
Application Number:
JP2008321466A
Publication Date:
November 24, 2011
Filing Date:
December 17, 2008
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L27/06; H01L21/8234; H01L21/8249
Domestic Patent References:
| JP11354657A | ||||
| JP8111508A | ||||
| JP8306880A | ||||
| JP6132525A | ||||
| JP61248459A | ||||
| JP2009290070A | ||||
| JP2008085307A | ||||
| JP2006066692A | ||||
| JP2005109394A | ||||
| JP2003158269A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa