Title:
半導体装置
Document Type and Number:
Japanese Patent JP6873801
Kind Code:
B2
Abstract:
To provide a semiconductor device including a first memory cell for holding first analog data, a second memory cell for holding reference analog data, and an offset circuit. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is supplied. The offset circuit supplies a third current corresponding to a differential current between the first current and the second current. The first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is supplied. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained. By providing a plurality of product-sum operation circuits that can be freely connected, a hierarchical neural network can be formed.
Inventors:
Yoshimoto Kurokawa
Application Number:
JP2017080216A
Publication Date:
May 19, 2021
Filing Date:
April 14, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G06G7/60; G11C11/54; H01L21/8242; H01L27/108
Domestic Patent References:
| JP2003167730A | ||||
| JP2015165558A | ||||
| JP2014143339A | ||||
| JP2015508588A | ||||
| JP2004186624A |
Foreign References:
| US20150381182 | ||||
| CN105340181A |