Title:
半導体装置
Document Type and Number:
Japanese Patent JP6917168
Kind Code:
B2
Abstract:
Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.
Inventors:
Uzumasa Munehiro
Yoshimoto Kurokawa
Yoshimoto Kurokawa
Application Number:
JP2017055303A
Publication Date:
August 11, 2021
Filing Date:
March 22, 2017
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H03K19/17728; H01L29/786
Domestic Patent References:
| JP201346181A | ||||
| JP2005269635A | ||||
| JP2014209714A |
Foreign References:
| US7761755 |